E33NCHA-LNN-NS-00

Brand: Kollmorgen

Type:E33NCHA-LNN-NS-00

Origin: the United States

Warranty: 365 days

Colour: new/used

Shipping method: Courier delivery

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Local Bus Timeout The MVME162 provides timeout functions in the VMEchip2 and the MCchip for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The timeout value is selectable by software for 8 μsec, 64 μsec, 256 μsec, or infinity. The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer. Refer to the VMEchip2 and MCchip descriptions in the MVME162 Embedded Controller Programmer’s Reference Guide for detailed programming information. The MCchip also provides local bus timeout logic for MVME162s without the optional VMEbus interface (i.e., without the VMEchip2). Timing Performance This section provides performance information for the MVME162. The MVME162 is designed to operate at 25 MHz.

Local Bus to DRAM Cycle Times The DRAM base address, array size, and device size are programmable. The DRAM controller assumes an interleaved architecture if the DRAM size requires eight physical devices (that is, when memory array size is 4MB and DRAM technology is 4 Mbits per device; or when memory array size is 16MB and DRAM technology is 16 Mbits per device.) Parity checking and parity exception action is also programmable. The DRAM array size and device size are initialized in the DRAM Space Size Register. Note TEA is the MC68040 bus error transaction signal. "With TEA" indicates that a bus error cycle occurs if a DRAM parity error was detected. EPROM/Flash Cycle Times The EPROM/Flash cycle time is programmable from 3 to 10 bus clocks/byte (4 bytes = 12 to 40). (The actual cycle time may vary depending on the device speed.) The data transfers are 32 bits wide. Refer to the MVME162 Embedded Controller Programmer’s Reference Guide. SCSI Transfers The MVME162 includes an SCSI mass storage bus interface with DMA controller. The SCSI DMA controller uses a FIFO buffer to interface the 8-bit SCSI bus to the 32-bit local bus. The FIFO buffer allows the SCSI DMA controller to efficiently transfer data to the local bus in four longword bursts.