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Intel core I3-3230m SR0WY AW8063801208001 mobile CPU 22 nm 3 m

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Product Details

General information

Type	CPU / Microprocessor
Family	Intel Core i5 Mobile
Processor number ?	i5-3230M
Part number	AW8063801208001
Frequency (GHz) ?	2.6
Frequency in IDA mode (GHz)	3.2
Clock multiplier ?	26
Package type	988-pin micro-FCPGA
Socket type	Socket G2 (rPGA988B)

Architecture / Microarchitecture / Other

CPUID	0306A9h
Core stepping	L1
Processor core	Ivy Bridge
Manufacturing technology (micron)	0.022
Number of cores	2
L2 cache size (KB) ?	512
L3 cache size (MB)	3
Features	AES AVX EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Hyper-Threading technology MMX SSE SSE2 SSE3 SSE4 SSSE3 Turbo Boost technology Virtualization technology (VT-d) Virtualization technology (VT-x)
Case temperature (°C) ?	105
Thermal Design Power (Watt) ?	35

In addition to the SR0WY S-Spec, this processor was also manufactured with one pre-production S-Spec number:

Stepping	S-Spec	AW8063801208001
E1	QD6E	+
L1	SR0WY	+

NOTE: Engineering and qualifications samples are marked with this color

Intel Core i5 Mobile i5-3230M SR0WY

Part number:	AW8063801208001
Frequency:	2594 MHz

Comment:
Submitted by:	CPU-World

General information
Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz
Cores:	2
Logical processors:	4
Processor type:	Original OEM Processor
CPUID signature:	306A9
Family:	6 (06h)
Model:	58 (03Ah)
Stepping:	9 (09h)
TLB/Cache details:	64-byte Prefetching Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries Data TLB: 4-KB Pages, 4-way set associative, 64 entries Instruction TLB: 4-KB pages, 4-way set associative, 64 entries L2 TLB: 1-MB, 4-way set associative, 64-byte line size Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache:	L1 data	L1 instruction	L2	L3
Size:	2 x 32 KB	2 x 32 KB	2 x 256 KB	3 MB
Associativity:	8-way set associative	8-way set associative	8-way set associative	12-way set associative
Line size:	64 bytes	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped	Inclusive Shared between all cores

Instruction set extensions		Additional instructions

MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
SSSE3		Enhanced REP MOVSB/STOSB
SSE4.1		FXSAVE/FXRSTORE
SSE4.2		MONITOR/MWAIT
AES		PCLMULDQ
AVX		POPCNT
F16C		RD/WR FSGSBASE instructions
		RDRAND
		RDTSCP
		SYSENTER/SYSEXIT
		XSAVE/XRESTORE states

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
Hyper-Threading Technology		CPL qualified debug store
Intel Virtualization		Debug store
Turbo Boost		Debugging extensions
Enhanced SpeedStep		Digital Thermal Sensor capability
		Extended xAPIC support
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Power Limit Notification capability
		Process context identifiers
		Self-snoop
		Supervisor Mode Execution Protection
		TSC rate is ensured to be invariant across all states
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Timestamp counter deadline
		Virtual 8086-mode enhancements
		xTPR Update Control

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