EG4S20BG256 On site programmable gate array (FPGA) ANLOGIC/Anlu Technology original stock

Flexible logical structure

19600 LUTs

Low power devices

Advanced 55nm low-power process

Static power consumption as low as 5mA

Rich on-chip storage space

64 9Kb embedded RAM (ERAM9K), 16 blocks

32Kb embedded RAM

64Mb SDRAM storage space

Maximum 156.8Kb distributed RAM

Configurable logic modules (PLBs)

Optimized LUT4/LUT5 combination design

Dual port distributed memory

Supports arithmetic logic operations

Fast carry chain logic

Embedded Multiplier

29 18 x 18 multipliers, supporting 9X9 mode

Up to 350MHz

Source synchronization input/output interface

The input/output unit contains DDR registers

Generic DDRx1

Generic DDRx2

High performance, flexible input/output buffer

Supports hot swapping

Configurable pull-up/pull-down mode

On chip 100 ohm differential resistance

Clock resources

16 global clocks

4 PLLs for frequency synthesis

5-way clock output

Frequency division coefficient from 1 to 128

Supports cascading of 5 clock outputs

Dynamic phase selection

Embedded hardcore IP

ADC

-12 bit successive approximation register type (SAR)

Up to 8 analog inputs

1MHz sampling rate (MSPS)

Integrated voltage monitoring module

Built in ring oscillator

Configuration mode

Main Mode Serial PROM (MS)

Main Mode Serial SPI (MSPI)

Serial from Mode (SS)

Main mode parallel x8 (MP)

Parallel x8 (SP) from mode

JTAG mode (IEEE-1532)

Supports dual boot and multi boot modes

BSCAN

Compatible with IEEE-1149.1

encapsulation

QFN88

FBGA256

CSG324