PH1A100SFG676 Field Programmable Gate Array (FPGA) ANLOGIC/Anlu Technology Low Price Processing

Distributed and embedded memory

The embedded block memory has a capacity of 20Kbits,

Pseudo dual port mode supports bit widths of 16K * 1 to 512 * 40

True dual port mode supports bit widths of 16K * 1 to 1K * 20

Supports ECC mode

Configurable logic modules (PLBs)

Autonomous and efficient dual LUT5 hybrid structure, supporting independent dual LUT4 functions

Dual port distributed memory

Supports arithmetic and logical operations

Fast carry chain logic

Dedicated shift register/latch

DSP

Can support two input adders, three input adders

Multipliers and arithmetic logic units.

Extended features: Multi bit wide operation, cascaded fast interconnection

Implement wide bit width addition, multiplication, and logical operations

Source synchronization input/output interface

HR I/O supports DDRx1 and DDRx2

HP I/O supports SERDESx1, SERDESx2

SERDESx3.5、SERDESx4、SERDESx5

High performance, flexible input/output buffer

Can be configured to support the following single end standards

HR I/O

- LVTTL33

- LVCMOS (3.3/2.5/1.8/1.5)

- HSTL-I (1.8V)

HP I/O

- LVCMOS (1.8/1.5/1.2V)

- HSTL-I (1.8V)

- SSTL (1.2V/1.35/1.5V)

- SSTL-I (1.8V)

- POD12

Can be configured to support the following differential standards

HR I/O

- LVDS (2.5/1.8V)

HP I/O

- LVDS (1.8V)

- DIFF-HSTL_I (1.8V)

- DIFFSTL (1.2V/1.35/1.5V)

- DIFF_SSTL_I (1.8V)

- DIFF-POD12

Supports 100 ohm terminal resistors within differential input chips

HR I/O supports hot swappable functionality

Configurable weak pull-up/pull-down mode

Clock resources

Provide efficient and flexible hierarchical clocks

-32 global clock network (GCLK) driving global

- Multi Region Clock (MLCLK) drives adjacent regions

- Regional Clock (LCLK) drives the local area

- I/O clock (IOCLK) provides high-speed I/O interfaces

High performance clock

Support PLLs for frequency and phase synthesis

- Single supports 7 clock outputs (supports reverse output)

- Duty cycle adjustment

- Phase adjustment

- Supports decimal frequency division

- Dynamic phase adjustment

- Dynamic configuration

- Clock Spread (SSC)

Configuration mode

Slave Serial

Active SPI (x1/x2/x4)

Slave Parallel x8/x16/x32

JTAG mode

SERDES

PH1A60 device does not support SERDES

The channel supports speeds from 1.2Gbps to 12.5Gbps

Integrate a hard core of PCI Express, supporting

GEN1/2/3， Supports X1, X2, and X4 modes

Support CPRI SGMII、JESD204B、SRIO、

XAUI、RXAUI、1000BASE-KX、10GBASE

Multiple protocols such as KX4 and CEI

MIPI DPHY-RX

2 sets of MIPI DPHY-RX, supporting up to 4 Lane modes

In MIPI mode, support for High Speed

HS data reception and data channel Lane0 Low

Power (hereinafter referred to as LP) data transmission and reception

Support dynamic sketch adjustment

Supports LVCMOS15/18 and LVDS18/25 input DDR

PH1A60 device does not support DDR

Supports DDR3 and DDR4 storage interfaces

Built in voltage and temperature detection module

Integrated high-precision voltage and temperature detection module, supporting electrical

Real time monitoring of pressure and temperature

BSCAN

Compatible with IEEE-1149.1

Enhanced security design protection

Each chip has a unique 64 bit DNA

SEU error detection and correction

Support single bit error detection and correction

Supports dual bit error detection

Multiple packaging forms

SFG900 Fine pitch BGA、Green，31mmx 31mm, 1mm pitch

SFG676 Fine pitch BGA、Green, 27mmx 27mm, 1mm pitch

SBG484 WBBGA、Green, 23mm x 23mm，

1mm pitch

GEG324 WBBGA、Green, 15mm x 15mm,

0.8mm pitch

SEG324 LFBGA 、 Green, 15mm x

15mm, 0.8mm pitch